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| PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 3803 Group (Spec.H QzROM version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0166-0110 Rev.1.10 Nov 14, 2005 DESCRIPTION The 3803 group (Spec.H QzROM version) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec.H QzROM version) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the serial interface functions, 8/16-bit timer, A/D converter and D/A converter. FEATURES * Basic machine-language instructions ................................. 71 * Minimum instruction execution time .......................... 0.24 s (at 16.8 MHz oscillation frequency) * Memory size QzROM .................................................... 16 K to 48 K bytes RAM ..................................................................... 2048 bytes * Programmable input/output ports ....................................... 56 * Software pull-up resistors ............................................ Built-in * Interrupts .............................................. 21 sources, 16 vectors (external 8, internal 12, software 1) * Timers ...................................................................... 16-bit x 1 8-bit x 4 (with 8-bit prescaler) * Serial interface ......... 8-bit x 2 (UART or Clock-synchronized) 8-bit x 1 (Clock-synchronized) * PWM ....................................... 8-bit x 1 (with 8-bit prescaler) * A/D converter ........................................ 10-bit x 16 channels (8-bit reading enabled) * D/A converter ............................................ 8-bit x 2 channels * Watchdog timer ....................................................... 16-bit x 1 * LED direct drive port..............................................................8 * Clock generating circuit ............................. Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) * Power source voltage [In high-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 4.0 to 5.5 V At 8.4 MHz oscillation frequency ...................... 2.7 to 5.5 V At 4.2 MHz oscillation frequency ...................... 2.2 to 5.5 V At 2.1 MHz oscillation frequency ...................... 2.0 to 5.5 V [In middle-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 2.7 to 5.5 V At 8.4 MHz oscillation frequency ...................... 2.2 to 5.5 V At 6.3 MHz oscillation frequency ...................... 1.8 to 5.5 V [In low-speed mode] At 32 kHz oscillation frequency......................... 1.8 to 5.5 V * Power dissipation In high-speed mode ........................................... 40 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................ 45 W (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) * Operating temperature range ............................. -20 to 85 C * Packages SP............................. PRDP0064BA-A (64-pin 750 mil SDIP) HP.................... PLQP0064KB-A (64-pin 10 x 10 mm LQFP) KP....................PLQP0064GA-A (64-pin 14 x 14 mm LQFP) APPLICATION Household products, Consumer electronics, etc. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 1 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Currently support products are listed below. Table 1 Support products QzROM size (bytes) RAM size ROM size for User in ( ) (bytes) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) Package PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PLQP0064KB-A PLQP0064GA-A PRDP0064BA-A PLQP0064KB-A PLQP0064GA-A PRDP0064BA-A PLQP0064KB-A PLQP0064GA-A PRDP0064BA-A PLQP0064KB-A PLQP0064GA-A PRDP0064BA-A PLQP0064KB-A PLQP0064GA-A Remarks Notice: This is not a final specification. Some parametric limits are subject to change. Product name M38039G4H-XXXHP M38039G4H-XXXKP M38039G6H-XXXHP M38039G6H-XXXKP M38039G8H-XXXHP M38039G8H-XXXKP M38039GCH-XXXHP M38039GCH-XXXKP M38039G4HSP M38039G4HHP M38039G4HKP M38039G6HSP M38039G6HHP M38039G6HKP M38039G8HSP M38039G8HHP M38039G8HKP M38039GCHSP M38039GCHHP M38039GCHKP NOTES: QzROM version (Programmed shipment) (1) 2048 QzROM version (blank) (2) 1. This means a shipment of which User ROM has been programmed. 2. The user ROM area of a blank product is blank. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 2 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. PIN CONFIGURATION (TOP VIEW) P10/INT41 P11/INT01 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P00/AN8 P01/AN9 P12 P13 P14 P15 P16 34 43 39 37 35 48 47 46 45 44 42 41 40 38 36 33 P17 32 31 30 29 28 27 26 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33 P32 P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 M38039GXH-XXXHP/KP M38039GXHHP/KP 25 24 23 22 21 20 19 18 17 10 11 12 13 14 15 P51/SOUT2 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P55/CNTR1 P54/CNTR0 P50/SIN2 P47/SRDY1/CNTR2 P45/TXD1 P44/RXD1 P52/SCLK2 Package type: PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) Fig 1. Table 2 3803 group (Spec.H QzROM version) pin configuration (PLQP0064KB-A/PLQP0064GA-A) List of package (Spec.H QzROM version) (PLQP0064KB-A/PLQP0064GA-A) Product name M38039G4H-XXXHP M38039G4HHP M38039G6H-XXXHP M38039G6HHP M38039G8H-XXXHP M38039G8HHP M38039GCH-XXXHP M38039GCHHP M38039G4H-XXXKP M38039G4HKP M38039G6H-XXXKP M38039G6HKP M38039G8H-XXXKP M38039G8HKP M38039GCH-XXXKP M38039GCHKP QzROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) 2048 32768 (32638) 49152 (49022) 16384 (16254) 24576 (24446) 2048 32768 (32638) 49152 (49022) RAM size (bytes) Remarks QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) QzROM version (Programmed shipment)(1) QzROM version (blank)(2) Package PLQP0064KB-A PLQP0064GA-A NOTES: 1. This means a shipment of which User ROM has been programmed. 2. The user ROM area of a blank product is blank. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 3 of 91 P53/SRDY2 P46/SCLK1 P56/PWM P43/INT2 16 1 2 3 4 5 6 7 8 9 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. PIN CONFIGURATION (TOP VIEW) VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 64 63 62 61 60 59 58 57 56 55 54 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) M38039GXHSP 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Package type: PRDP0064BA-A (64P4B) Fig 2. Table 3 3803 group (Spec.H QzROM version) pin configuration (PRDP0064BA-A) List of package (Spec.H QzROM version) (PRDP0064BA-A) Product name M38039G4HSP QzROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 2048 QzROM version (blank)(1) RAM size (bytes) Remarks Package PRDP0064BA-A M38039G6HSP M38039G8HSP M38039GCHSP NOTES: 1. The user ROM area of a blank product is blank. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 4 of 91 Fig 3. Reset input VSS VCC 1 26 27 32 FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0064BA-A) RESET CNVSS Clock input XIN Clock output XOUT Sub-clock Sub-clock input output XCIN XCOUT 30 31 28 29 3803 Group (Spec.H QzROM version) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Data bus Functional block diagram CPU Clock generating circuit X Prescaler 12 (8) RAM ROM A Timer 1 (8) Timer 2 (8) Timer X (8) Timer Y (8) Timer Z (16) CNTR2 Page 5 of 91 Y Prescaler X (8) S CNTR0 PCH PS CNTR1 PCL Prescaler Y (8) 0 A/D converter (10) SI/O2 (8) SI/O1 (8) PWM (8) D/A converter 2 (8) D/A converter 1 (8) SI/O3 (8) INT3 INT01 INT41 PRELIMINARY P6 (8) P5 (8) P4 (8) INT00 INT1 INT2 INT40 P3 (8) P2 (8) P1 (8) P0 (8) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VREF AVss Notice: This is not a final specification. Some parametric limits are subject to change. I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P 2 (LED drive) I/O port P 1 I/O port P 0 PRELIMINARY 3803 Group (Spec.H QzROM version) PIN DESCRIPTION Table 4 Pin VCC, VSS CNVSS Notice: This is not a final specification. Some parametric limits are subject to change. Pin description Name Power source CNVSS input Functions * Apply voltage of 1.8 V - 5.5 V to VCC, and 0 V to VSS. * This pin controls the operation mode of the chip and is shared with the VPP pin which is the power source input pin for programming the built-in QzROM. * Normally connected to VSS. * Reference voltage input pin for A/D and D/A converters. * Analog power source input pin for A/D and D/A converters. * Connect to VSS. * Reset input pin for active "L". * Input and output pins for the clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * 8-bit CMOS I/O port. * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level. * CMOS 3-state output structure. * Pull-up control is enabled in a bit unit. * P20 - P27 (8 bits) are enabled to output large current for LED drive. * A/D converter input pin * Interrupt input pin Function except a port function VREF AVSS RESET XIN XOUT P00/AN8- P07/AN15 P10/INT41 P11/INT01 P12-P17 P20-P27 P30/DA1 P31/DA2 P32, P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 P47/SRDY1/CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0- P67/AN7 Reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 * D/A converter input pin * 8-bit CMOS I/O port. * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level. * Serial I/O3 function pin * P30, P31, P34 - P37 are CMOS 3-state output structure. * P32, P33 are N-channel open-drain output structure. * Pull-up control of P30, P31, P34 - P37 is enabled in a bit unit. * 8-bit CMOS I/O port. * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level. * CMOS 3-state output structure. * Pull-up control is enabled in a bit unit. * Interrupt input pin * Sub-clock generating I/O pin (resonator connected) * Interrupt input pin * Serial I/O1 function pin I/O port P4 * Serial I/O1, timer Z function pin I/O port P5 * Serial I/O2 function pin * Timer X function pin * Timer Y function pin * PWM output pin * Interrupt input pin I/O port P6 * A/D converter input pin Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 6 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) PART NUMBERING Notice: This is not a final specification. Some parametric limits are subject to change. Product name M3803 9 G C H- XXX SP Package type SP : PRDP0064BA-A HP : PLQP0064KB-A KP : PLQP0064GA-A ROM number Omitted in blank version. -: standard "-" is omitted in the shipped in blank version. H-: Partial specification changed version. QzROM size 1: 4096 bytes 2: 8192 bytes 3: 12288 bytes 4: 16384 bytes 5: 20480 bytes 6: 24576 bytes 7: 28672 bytes 8: 32768 bytes 9: 36864 bytes A: 40960 bytes B: 45056 bytes C: 49152 bytes D: 53248 bytes E: 57344 bytes F: 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. Memory type G: QzROM version RAM size 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes Fig 4. Part numbering Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 7 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) GROUP EXPANSION Renesas Technology expands the 3803 group (Spec.H QzROM version) as follows. Memory Type Support for QzROM version. Notice: This is not a final specification. Some parametric limits are subject to change. Memory Size * QzROM size ................................................ 16 K to 48 K bytes * RAM size..................................................................2048 bytes Packages * PRDP0064BA-A ..................64-pin shrink plastic-molded DIP * PLQP0064KB-A ...............0.5 mm-pitch plastic molded LQFP * PLQP0064GA-A ...............0.8 mm-pitch plastic molded LQFP Memory Expansion Plan ROM size (bytes) As of Sep. 2005 Under development 48K M38039GCH Under development 32K M38039G8H Under development 24K M38039G6H Under development 16K M38039G4H 640 1024 1536 RAM size (bytes) 2048 Notes 1: Products under development: the development schedule and specification may be revised without notice. Fig 5. Memory expansion plan Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 8 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) GROUP DESCRIPTION Notice: This is not a final specification. Some parametric limits are subject to change. The QzROM version of 3803 group (Spec.H) is under development. The mask ROM version and the flash memory version are mass production. Currently support products are listed below. Table 5 Support products (mask ROM version and flash memory version of Spec.H) ROM/flash memory size (bytes) ROM size for User in ( ) 16384 (16254) RAM size (bytes) Package PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PTLG0064JA-A (64F0G) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PTLG0064JA-A (64F0G) PRDP0064BA-A (64P4B) PRQP0064GA-A (64P6N-A) PLQP0064KB-A (64P6Q-A) Remarks Product name M38034M4H-XXXSP M38034M4H-XXXFP M38034M4H-XXXHP M38034M4H-XXXKP M38037M6H-XXXSP M38037M6H-XXXFP M38037M6H-XXXHP M38037M6H-XXXKP M38037M8H-XXXSP M38037M8H-XXXFP M38037M8H-XXXHP M38037M8H-XXXKP M38039MCH-XXXSP M38039MCH-XXXFP M38039MCH-XXXHP M38039MCH-XXXKP M38039MFH-XXXSP M38039MFH-XXXFP M38039MFH-XXXHP M38039MFH-XXXKP M38039MFH-XXXWG M38039FFHSP M38039FFHFP M38039FFHHP M38039FFHKP M38039FFHWG M38039FFSP M38039FFFP M38039FFHP 640 24576 (24446) 1024 32768 (32638) 1024 Mask ROM version 49152 (49022) 2048 61440 (61310) 2048 Flash memory version (VCC=2.7-5.5V) 61440 2048 Flash memory version (VCC=4.0-5.5V) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 9 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803 group (Spec.H QzROM version) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. Notice: This is not a final specification. Some parametric limits are subject to change. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0", the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure.7. Store registers other than those described in Figure.6 with program when the user needs them during interrupts or subroutine calls (see Table 6). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 A b7 X b7 Y b7 S b15 PCH b7 PCL b0 Accumulator b0 Index Register X b0 Index Register Y b0 Stack Pointer b0 Program Counter b7 b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig 6. 740 Family CPU register structure Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 10 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. On-going Routine Interrupt request (Note) M(S)(PCH) (S)(S) - 1 Execute JSR M(S)(PCL) Push Return Address on Stack Push Return Address on Stack M(S)(PCH) (S)(S) - 1 (S)(S) - 1 M(S)(PS) Push Contents of Processor Status Register on Stack M(S)(PCL) (S)(S) - 1 (S)(S) - 1 Interrupt Service Routine ..... Subroutine ..... Execute RTI (S)(S) + 1 I Flag is Set from "0" to "1" Fetch the Jump Vector Execute RTS (S)(S) + 1 (PS)M(S) (PCL)M(S) (S)(S) + 1 (S)(S) + 1 (PCL)M(S) (PCH)M(S) (S)(S) + 1 (PCH)M(S) POP Return Address from Stack POP Contents of Processor Status Register from Stack POP Return Address from Stack Note : Condition for acceptance of an interrupt Interrupt enable flag is "1" Interrupt disable flag is "0" Fig 7. Table 6 Register push and pop at interrupt generation and subroutine call Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Accumulator Processor status register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 11 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. Notice: This is not a final specification. Some parametric limits are subject to change. Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to - 128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 7 Set and clear instructions of each bit of processor status register C flag SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Set instruction Clear instruction Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 12 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B16. Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 1 CPU mode register (CPUM: address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0: Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig 8. Structure of CPU mode register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 13 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting "1" to bit 0 of MISRG (address 001016). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure.9 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a sub-clock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3803 group (Spec.H QzROM version) has the built-in function which automatically switches from low to middle-speed mode by program. Notice: This is not a final specification. Some parametric limits are subject to change. * Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to "1" in the condition that the middlespeed mode automatic switch set bit is "1" while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). b7 b0 MISRG MISRG: address 001016) Oscillation stabilizing time set after STP instruction released bit 0 : Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1 : Automatically set disabled Middle-speed mode automatic switch set bit 0 : Not set automatically 1 : Automatic switching enabled (Note) Middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0 : Invalid 1 : Automatic switch start (Note) Not used (return "0" when read) (Do not write "1" to this bit) Note : When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B16) change. Fig 9. Structure of MISRG Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 14 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) MEMORY * Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. * RAM The RAM is used for data storage and for stack area of subroutine calls and interrupts. * ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. In the QzROM version, 1 byte of address FFDB16 is also a reserved area. * Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. * Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. * Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Notice: This is not a final specification. Some parametric limits are subject to change. * ROM Code Protect Address (address FFDB16) Address FFDB16, which is the reserved ROM area of QzROM, is the ROM code protect address. "0016" or "FE16" is written into this address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When "0016" or "FE16" is set to the ROM code protect address, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. The protect can be performed, dividing twice. The protect area 1 is from the beginning address of ROM to address "EFFF16". As for the QzROM product shipped after writing, "0016" (protect enabled to all area), "FE16" (protect enabled to the protect area 1) or "FF16" (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of "0016", "FE16" or "FF16" can be selected as ROM option setup ("MASK option" written in the mask file converter) when ordering. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 User ROM area Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 000016 SFR area 004016 RAM 010016 XXXX16 083F16 084016 0FDF16 0FE016 0FFF16 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 YYYY16 Reserved ROM area (128 bytes) ZZZZ16 Protect area 1 Zero page Reserved area Not used SFR area Not used Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 ROM EFFF16 F00016 FF0016 FFDB16 FFDC16 FFFE16 FFFF16 Reserved ROM area (ROM code protect address) Special page Interrupt vector area Reserved ROM area Fig 10. Memory map diagram Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 15 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Timer 12, X count source selection register (T12XCSS) 000F16 Timer Y, Z count source selection register (TYZCSS) 001016 MISRG 001116 Reserved * 001216 Reserved * 001316 Reserved * 001416 Reserved * 001516 Reserved * 001616 Reserved * 001716 Reserved * 001816 Transmit/Receive buffer register 1 (TB1/RB1) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART1 control register (UART1CON) 001C16 Baud rate generator (BRG1) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Watchdog timer control register (WDTCON) 001F16 Serial I/O2 register (SIO2) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) AD conversion register 1 (AD1) DA1 conversion register (DA1) DA2 conversion register (DA2) AD conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 003F16 Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FE016 Reserved * 0FE116 Reserved * 0FE216 Reserved * 0FE316 Reserved * 0FE416 Reserved * 0FE516 Reserved * 0FE616 Reserved * 0FE716 Reserved * 0FE816 Reserved * 0FE916 Reserved * 0FEA16 Reserved * 0FEB16 Reserved * 0FEC16 Reserved * 0FED16 Reserved * 0FEE16 Reserved * 0FEF16 Reserved * 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) *Reserved area: Do not write any data to these addresses, because these areas are reserved. Fig 11. Memory map of special function register (SFR) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 16 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. Notice: This is not a final specification. Some parametric limits are subject to change. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. By setting the port P0 pull-up control register (address 0FF016) to the port P6 pull-up control register (address 0FF616) ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports. Table 8 I/O port function Pin Input/ I/O Structure Non-Port Function Output Port P0 Input/output, CMOS compatible A/D converter input input level Port P1 individual External interrupt input bits CMOS 3-state output Name Ref. No. AD/DA control register (1) Interrupt edge selection register (2) (3) AD/DA control register (4) (5) Related SFRs P00/AN8-P07/AN15 P10/INT41 P11/INT01 P12-P17 P20/LED0-P27/LED7 Port P2 Port P3 P30/DA1 P31/DA2 P32, P33 D/A converter output CMOS compatible input level N-channel open-drain output CMOS compatible Serial I/O3 function I/O input level CMOS 3-state output External interrupt input Sub-clock generating circuit External interrupt input Serial I/O1 function I/O P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 P47/SRDY1/CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0-P67/AN7 Serial I/O3 control register UART3 control register Port P4 (6) (7) (8) (9) Interrupt edge selection register (10) CPU mode register (11) Interrupt edge selection register (2) (6) (7) (8) (12) (13) (14) (15) (16) (17) Serial I/O1 control register UART1 control register Serial I/O1 control register Timer Z mode register Serial I/O2 control register Port P5 Serial I/O1 function I/O Timer Z function I/O Serial I/O2 function I/O Timer X, Y function I/O PWM output External interrupt input A/D converter input Timer XY mode register Port P6 PWM control register (18) Interrupt edge selection register (2) AD/DA control register (1) NOTES: 1. Refer to the applicable sections how to use double-function ports as function I/O ports. 2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 17 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. (1) Ports P0, P6 Pull-up control bit (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit Interrupt input (3) Ports P12 to P17, P2 Pull-up control bit (4) Ports P30, P31 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch D/A converter output DA1 output enable bit (P30) DA2 output enable bit (P31) (5) Ports P32, P33 (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 Pull-up control bit Serial I/O enable bit Transmit enable bit Direction register Data bus P-channel output disable bit (8) Ports P36, P46 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Pull-up control bit Port latch Serial I/O output Serial I/O clock output Serial I/O external clock input Fig 12. Port block diagram (1) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 18 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. (9) Port P37 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Direction register (10) Port P40 Pull-up control bit Port XC switch bit Direction register Data bus Data bus Port latch Port latch INT40 Interrupt input Serial I/O3 ready output Port XC switch bit (11) Port P41 Pull-up control bit Port XC switch bit Direction register (12) Port P47 Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register INT00 Interrupt input Port XC switch bit Sub-clock generating circuit input Pull-up control bit Data bus Port latch Data bus Port latch Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 Pull-up control bit Direction register (14) Port P51 Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register P-channel output disable bit Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig 13. Port block diagram (2) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 19 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. (15) Port P52 Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register (16) Port P53 Pull-up control bit SRDY2 output enable bit Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 Pull-up control bit (18) Port P56 Pull-up control bit PWM function enable bit Direction register Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output PWM output CNTR Interrupt input Fig 14. Port block diagram (3) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 20 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig 15. Structure of port pull-up control register (1) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 21 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return "0" when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig 16. Structure of port pull-up control register (2) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 22 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig 17. Structure of port pull-up control register (3) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 23 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. Fig 18. Structure of port pull-up control register (4) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 24 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) INTERRUPTS The 3803 group (Spec.H QzROM version)'s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. * Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. * Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. * Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916). 1. INT0 or Timer Z 2. CNTR1 or Serial I/O3 reception 3. Serial I/O2 or Timer Z 4. INT4 or CNTR2 5. A/D converter or serial I/O3 transmission * External Interrupt Pin Selection The occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or input from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16). Notice: This is not a final specification. Some parametric limits are subject to change. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 25 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 9 Interrupt vector addresses and priority Priority 1 2 Vector Interrupt Request Generating Addresses(1) Conditions High Low FFFD16 FFFC16 At reset FFFB16 FFFA16 At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Interrupt Source Reset(2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 INT3 INT4 CNTR2 A/D converter Serial I/O3 transmission 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 6 7 8 9 10 11 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected 12 FFE716 FFE616 13 14 15 FFE516 FFE316 FFE116 FFE416 FFE216 FFE016 External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected 16 FFDF16 FFDE16 BRK instruction 17 FFDD16 FFDC16 NOTES: 1. Vector addresses contain interrupt jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Non-maskable software interrupt Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 26 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig 19. Interrupt control Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 27 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns "0" when read) INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns "0" when read) 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL : address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write "1" to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write "1" to these bits.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write "1" to this bit.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A/D converter interrupt 1 : Serial I/O3 transmit interrupt Fig 20. Structure of interrupt-related registers Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 28 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) TIMERS * 8-bit Timers The 3803 group (Spec.H QzROM version) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to "1". * Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B16). When these bits are "00" (high-speed mode) or "01" (middle-speed mode), XIN is selected. When these bits are "10" (low-speed mode), XCIN is selected. * Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). * Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. * Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). Notice: This is not a final specification. Some parametric limits are subject to change. * Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode * Mode selection This mode can be selected by setting "00" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). * Explanation of operation The timer count operation is started by setting "0" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse Output Mode * Mode selection This mode can be selected by setting "01" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). * Explanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. Switching the CNTR0 or CNTR1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. * Precautions Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to output in this mode. (3) Event Counter Mode * Mode selection This mode can be selected by setting "10" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). * Explanation of operation The operation is the same as the timer mode's except that the timer counts signals input from the CNTR0 or CNTR1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. * Precautions Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to input in this mode. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 29 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) (4) Pulse Width Measurement Mode * Mode selection This mode can be selected by setting "11" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). * Explanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "1", the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" term). When it is "0", the timer counts during the term of one rising edge input until the next falling edge input ("H" term). * Precautions Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to input in this mode. The count operation can be stopped by setting "1" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to "1" each time the timer underflows. * Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Notice: This is not a final specification. Some parametric limits are subject to change. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 30 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. XIN "00" "11" (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Count source selection bit Data bus XCIN "10" Clock for timer 12 Clock for timer Y Main clock division ratio selection bits Clock for timer X Prescaler X latch (8) f(XCIN) Pulse width Timer mode measurement Pulse output mode mode Prescaler X (8) Timer X latch (8) Timer X (8) P54/CNTR0 CNTR0 active edge switch bit "0" To timer X interrupt request bit Event counter mode Timer X count stop bit To CNTR0 interrupt request bit "1" CNTR0 active edge switch bit "1" Q "0" Q Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P54 direction register Port P54 latch Pulse output mode Data bus Count source selection bit Clock for timer Y f(XCIN) Prescaler Y latch (8) Pulse width Timer mode measurement Pulse output mode mode Prescaler Y (8) Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit P55/CNTR1 CNTR1 active edge switch bit "0" "1" Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge switch bit "1" Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode Port P55 direction register Port P55 latch Pulse output mode "0" Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig 21. Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 31 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5 b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig 22. Structure of timer XY mode register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 32 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) 1010: 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used b7 b0 Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used Fig 23. Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 33 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) * 16-bit Timer The timer Z is a 16-bit timer. When the timer reaches "000016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to "1". When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). (1) Timer mode * Mode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. * Interrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to "1". * Explanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting "0" to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches "000016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Notice: This is not a final specification. Some parametric limits are subject to change. (2) Event counter mode * Mode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "1" to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. * Interrupt The interrupt at an underflow is the same as the timer mode's. * Explanation of operation The operation is the same as the timer mode's. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure.26 shows the timing chart of the timer/event counter mode. (3) Pulse output mode * Mode selection This mode can be selected by setting "001" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. * Interrupt The interrupt at an underflow is the same as the timer mode's. * Explanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. * Precautions The double-function port of CNTR2 pin and port P47 is automatically set to the timer pulse output port in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure.27 shows the timing chart of the pulse output mode. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 34 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) (4) Pulse period measurement mode * Mode selection This mode can be selected by setting "010" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. * Interrupt The interrupt at an underflow is the same as the timer mode's. When the pulse period measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". * Explanation of operation The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is "1", the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and "FFFF16" is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. * Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period m e a s u r em e n t d e p e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure.28 shows the timing chart of the pulse period measurement mode. Notice: This is not a final specification. Some parametric limits are subject to change. (5) Pulse width measurement mode * Mode selection This mode can be selected by setting "011" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. * Interrupt The interrupt at an underflow is the same as the timer mode's. When the pulse widths measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". * Explanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one rising edge input to the next falling edge input ("H" term). When it is "1", the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input ("L" term). When the valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch. When the valid edge of measurement completion/start is detected, "FFFF16" is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and "FFFF16" is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. * Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width m e a s u r em e n t d ep e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure.29 shows the timing chart of the pulse width measurement mode. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 35 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) (6) Programmable waveform generating mode * Mode selection This mode can be selected by setting "100" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. * Interrupt The interrupt at an underflow is the same as the timer mode's. * Explanation of operation The operation is the same as the timer mode's. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. * Precautions The double-function port of CNTR2 pin and port P47 is automatically set to the programmable waveform generating port in this mode. Figure.30 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode * Mode selection This mode can be selected by setting "101" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). * Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. * Interrupt The interrupt at an underflow is the same as the timer mode's. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is "0", the falling edge active is selected; when it is "1", the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to "1". * Explanation of operation 1. "H" one-shot pulse; Bit 5 of timer Z mode register = "0" The output level of the CNTR2 pin is initialized to "L" at mode selection. When trigger generation (input signal to INT1 pin) is detected, "H" is output from the CNTR2 pin. When an underflow occurs, "L" is output. The "H" one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, although "H" is output from the CNTR2 pin, "H" output state continues because an underflow does not occur. Notice: This is not a final specification. Some parametric limits are subject to change. 2. "L" one-shot pulse; Bit 5 of timer Z mode register = "1" The output level of the CNTR2 pin is initialized to "H" at mode selection. When trigger generation (input signal to INT1 pin) is detected, "L" is output from the CNTR2 pin. When an underflow occurs, "H" is output. The "L" one-shot pulse width is set by the setting value to the timer Z loworder and high-order. When trigger generating is detected during timer count stop, although "L" is output from the CNTR2 pin, "L" output state continues because an underflow does not occur. * Precautions Set the double-function port of INT1 pin and port P42 to input in this mode. The double-function port of CNTR2 pin and port P47 is automatically set to the programmable one-shot generating port in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure.31 shows the timing chart of the programmable one-shot generating mode. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 36 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. P42/INT1 Programmable one-shot generating mode CNTR2 active edge Data bus switch bit Programmable one-shot "1" generating mode Programmable one-shot generating circuit "0" To INT1 interrupt request bit Programmable waveform generating mode Output level latch D T Pulse output mode S Q T "001" "100" "101" Q Q CNTR2 active edge switch bit "0" "1" Pulse output mode Timer Z operating mode bits Port P47 latch Port P47 direction register Timer Z low-order latch Timer Z low-order Timer Z high-order latch Timer Z high-order To timer Z interrupt request bit Pulse period measurement mode Pulse width measurement mode Edge detection circuit To CNTR2 interrupt request bit "1" P47/CNTR2 "0" CNTR2 active edge switch bit XIN Clock for timer z "1" f(XCIN) "0" Timer Z count stop bit Timer/Event counter mode switch bit XCIN Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig 24. Block diagram of timer Z Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 37 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2 b1 b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : "L" output 1 : "H" output CNTR2 active edge switch bit 0 : *Event counter mode: Count at rising edge *Pulse output mode: Start outputting "H" *Pulse period measurement mode: Measurement between two falling edges *Pulse width measurement mode: Measurement of "H" term *Programmable one-shot generating mode: After start outputting "L", "H" one-shot pulse generated *Interrupt at falling edge 1 : *Event counter mode: Count at falling edge *Pulse output mode: Start outputting "L" *Pulse period measurement mode: Measurement between two rising edges *Pulse width measurement mode: Measurement of "L" term *Programmable one-shot generating mode: After start outputting "H", "L" one-shot pulse generated *Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set "0" to this bit. Fig 25. Structure of timer Z mode register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 38 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig 26. Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig 27. Timing chart of pulse output mode Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 39 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request CNTR2 CNTR2 T2 T3 FFFF16 TR Fig 28. Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of "L" width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig 29. Timing chart of pulse width measurement mode (Measuring "L" term) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 40 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L TR T1 TR CNTR2 T3 TR T2 TR CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig 30. Timing chart of programmable waveform generating mode FFFF16 L Signal input from INT1 pin Signal output from CNTR2 pin TR TR TR L CNTR2 L CNTR2 L L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig 31. Timing chart of programmable one-shot generating mode ("H" one-shot pulse generating) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 41 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) SERIAL INTERFACE * Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Notice: This is not a final specification. Some parametric limits are subject to change. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O1 control register Receive buffer full flag (RBF) Receive interrupt request (RI) Address 001A16 Address 001816 Receive buffer register 1 P44/RXD1 Receive shift register 1 Shift clock Clock control circuit P46/SCLK1 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 Address 001C16 P47/SRDY1 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P45/TXD1 Transmit shift register 1 Transmit buffer register 1 Address 001816 Data bus Fig 32. Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD1 Serial input RXD1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1". Fig 33. Operation of clock synchronous serial I/O1 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 42 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Notice: This is not a final specification. Some parametric limits are subject to change. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) OE P44/RXD1 ST detector Address 001816 Receive buffer register 1 Character length selection bit 7 bits 8 bits PE FE SP detector Receive shift register 1 1/16 UART1 control register Clock control circuit Serial I/O1 synchronous clock selection bit Address 001B16 P46/SCLK1 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 P45/TXD1 Character length selection bit Transmit buffer register 1 Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register 1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Fig 34. Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 ST D0 TBE=0 TBE=1 TSC=1* ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP Receive buffer read signal RBF=0 RBF=1 Serial input RXD1 RBF=1 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1", can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig 35. Operation of UART serial I/O1 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 43 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Notice: This is not a final specification. Some parametric limits are subject to change. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 44 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O1 pins) b7 b0 UART1 control register (UART1CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig 36. Structure of serial I/O1 control registers Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 45 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation * Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". * Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TXD1, RXD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. 2.2 Stop of receive operation * Note Clear the receive enable bit to "0" (receive disabled). 2.3 Stop of transmit/receive operation * Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". * Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TXD1, RXD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. * Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 46 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) 3. SRDY1 output of reception side * Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O1 control register again * Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0". Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Notice: This is not a final specification. Some parametric limits are subject to change. 7. Transmit interrupt request when transmit enable bit is set * Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). 2. Set the transmit enable bit to "1". 3. Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instruction has executed. 4. Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). * Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" 5.Data transmission control with referring to transmit shift register completion flag * Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected * Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK1 input level. Also, write data to the transmit buffer register at "H" of the SCLK1 input level. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 47 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) * Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register (address 001F16). [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2, SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig 37. Structure of Serial I/O2 control register 1/8 1/16 Internal synchronous clock selection bits Data bus Divider P53 latch "0" Serial I/O2 synchronous clock selection bit "1" SCLK2 f(XIN) (f(XCIN) in low-speed mode) 1/32 1/64 1/128 1/256 P53/SRDY2 SRDY2 Synchronization circuit "1" SRDY2 output enable bit External clock "0" P52 latch "0" P52/SCLK2 "1" Serial I/O2 port selection bit P51 latch "0" Serial I/O counter 2 (3) Serial I/O2 interrupt request P51/SOUT2 "1" Serial I/O2 port selection bit P50/SIN2 Serial I/O2 register (8) Address 001F16 Fig 38. Block diagram of serial I/O2 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 48 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or (f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig 39. Timing of serial I/O2 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 49 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) * Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation. Notice: This is not a final specification. Some parametric limits are subject to change. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Receive buffer full flag (RBF) Receive interrupt request (RI) Address 003216 Address 003016 Receive buffer register 3 P34/RXD3 Receive shift register 3 Shift clock Clock control circuit P36/SCLK3 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 Address 002F16 P37/SRDY3 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 P35/TXD3 Transmit shift register 3 Transmit buffer register 3 Address 003016 Data bus Fig 40. Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD3 Serial input RXD3 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1". Fig 41. Operation of clock synchronous serial I/O3 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 50 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit (b6) of the serial I/O3 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Notice: This is not a final specification. Some parametric limits are subject to change. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Serial I/O3 control register Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) OE P34/RXD3 ST detector Address 003016 Receive buffer register 3 Character length selection bit 7 bits 8 bits PE FE SP detector Receive shift register 3 1/16 UART3 control register Clock control circuit Serial I/O3 synchronous clock selection bit Address 003316 P36/SCLK3 Frequency division ratio 1/(n+1) Baud rate generator 3 Address 002F16 ST/SP/PA generator 1/16 P35/TXD3 Character length selection bit Transmit buffer register 3 Address 003016 Data bus Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Transmit shift register 3 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Fig 42. Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD3 ST D0 TBE=0 TBE=1 TSC=1* ST D0 D1 SP * Generated at 2nd bit in 2-stop-bit mode D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD3 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1", can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig 43. Operation of UART serial I/O3 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 51 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Notice: This is not a final specification. Some parametric limits are subject to change. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 52 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 Serial I/O3 status register (SIO3STS : address 003116) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O3 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O3 is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O3 disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O3 enabled (pins P34 to P37 operate as serial I/O3 pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig 44. Structure of serial I/O3 control registers Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 53 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation * Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". * Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TXD3, RXD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. 2.2 Stop of receive operation * Note Clear the receive enable bit to "0" (receive disabled). 2.3 Stop of transmit/receive operation * Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". * Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TXD3, RXD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. * Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 54 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) 3. SRDY3 output of reception side * Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY3 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O3 control register again * Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0". Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Notice: This is not a final specification. Some parametric limits are subject to change. 7. Transmit interrupt request when transmit enable bit is set * Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O3 transmit interrupt enable bit to "0" (disabled). 2. Set the transmit enable bit to "1". 3. Set the serial I/O3 transmit interrupt request bit to "0" after 1 or more instruction has executed. 4. Set the serial I/O3 transmit interrupt enable bit to "1" (enabled). * Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" 5.Data transmission control with referring to transmit shift register completion flag * Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected * Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK3 input level. Also, write data to the transmit buffer register at "H" of the SCLK input level. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 55 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) PULSE WIDTH MODULATION (PWM) The 3803 group (Spec.H QzROM version) has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. * Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255): PWM period = 255 x (n+1) / f(XIN) = 31.875 x (n+1) s (when f(XIN) = 8 MHz, count source selection bit = "0") Output pulse "H" term = PWM period x m / 255 = 0.125 x (n+1) x m s (when f(XIN) = 8 MHz, count source selection bit = "0") Notice: This is not a final specification. Some parametric limits are subject to change. * PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 x m x (n+1) 255 s PWM output T = [31.875 x (n+1)] s m : Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source selection bit = "0") Fig 45. Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit XIN (XCIN at lowspeed mode) "0" "1" PWM prescaler PWM register latch Port P56 PWM register 1/2 Port P56 latch PWM function enable bit Fig 46. Block diagram of PWM function Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 56 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0 PWM control register (PWMCON: address 002B16) PWM function enable bit 0 : PWM disabled 1 : PWM enabled Count source selection bit 0 : f(XIN) (f(XCIN) at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return "0" when read) Fig 47. Structure of PWM control register A PWM output T PWM register write signal PWM prescaler write signal B C B C T = T2 T T2 (Changes "H" term from "A" to " B".) (Changes PWM period from "T" to "T2".) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig 48. PWM output timing when PWM register or PWM prescaler is changed n+1 ---------------------- sec 2xf ( XIN ) n + 1--------------- sec f ( XIN ) (Count source selection bit = 0, where n is the value set in the prescaler) (Count source selection bit = 1, where n is the value set in the prescaler) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 57 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) A/D CONVERTER [AD Conversion Register 1, 2 (AD1, AD2)] 003516, 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 is the conversion mode selection bit. When this bit is set to "0", the A/D converter becomes the 10-bit A/D mode. When this bit is set to "1", that becomes the 8-bit A/D mode. The conversion result of the 8-bit A/D mode is stored in the AD conversion register 1. As for 10-bit A/D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure.50). As for 10-bit A/D mode, the 8-bit reading inclined to MSB is performed when reading the AD converter register 1 after A/D conversion is started; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading inclined to LSB is performed. [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A/D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at "0" during an A/D conversion, and changes to "1" when an A/D conversion ends. Writing "0" to this bit starts the A/D conversion. * Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF into 1024, and that outputs the comparison voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode). The A/D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. * 10-bit A/D mode (10-bit reading) VREF Vref = ------------- x n (n = 0 - 1023) 1024 * 10-bit A/D mode (8-bit reading) VREF Vref = ------------- x n (n = 0 - 255) 256 * 8-bit A/D mode VREF Vref = ------------- x n (n - 0.5) (n = 1 - 255) 256 =0 (n = 0) Notice: This is not a final specification. Some parametric limits are subject to change. * Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. * Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A/D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1: 0: 1: 0: 1: 0: 1: P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 or or or or or or or or P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Not used (returns "0" when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig 49. Structure of AD/DA control register 8-bit reading (Read only address 003516) AD conversion register 1 (AD1: address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 10-bit reading (Read address 003816 before 003516) AD conversion register 2 (AD2: address 003816) AD conversion register 1 (AD1: address 003516) b7 0 b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become "0" at reading. Fig 50. Structure of 10-bit A/D mode reading Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 58 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Data bus AD/DA control register b7 (Address 003416) 4 b0 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 A/D control circuit AD conversion register 2 AD conversion register 1 10 Resistor ladder A/D converter interrupt request Comparator Channel selector (Address 003816) (Address 003516) VREF AVSS Fig 51. Block diagram of A/D converter Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 59 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) D/A CONVERTER The 3803 group (Spec.H QzROM version) has two internal D/A converters (DA1 and DA2) with 8-bit resolution. The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to "1". When using the D/A converter, the corresponding port direction register bit (P30/DA1 or P31/DA2) must be set to "0" (input status). The output analog voltage V is determined by the value n (decimal notation) in the DA conversion register as follows: V = VREFx n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are cleared to "0016", and the DA output enable bits are cleared to "0", and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. Notice: This is not a final specification. Some parametric limits are subject to change. DA1 conversion register (8) DA1 output enable bit Data bus R-2R resistor ladder P30/DA1 DA2 conversion register (8) DA2 output enable bit R-2R resistor ladder P31/DA2 Fig 52. Block diagram of D/A converter "0" DA1 output enable bit R P30/DA1 "1" 2R MSB DA1 conversion register "0" "1" R 2R R 2R R 2R R 2R R 2R R 2R 2R 2R LSB AVSS VREF Fig 53. Equivalent connection circuit of D/A converter (DA1) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 60 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. * Watchdog Timer Initial Value Watchdog timer L is set to "FF16" and watchdog timer H is set to "FF16" by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the abovementioned value will be set to each timer. * Watchdog Timer Operations The watchdog timer stops at reset and starts to count down by writing to the watchdog timer control register (address 001E16). An internal reset occurs at an underflow of the watchdog timer H. The reset is released after waiting for a reset release time and the program is processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. If writing to the watchdog timer control register is not performed once, the watchdog timer does not function. Notice: This is not a final specification. Some parametric limits are subject to change. * Bit 6 of Watchdog Timer Control Register * When bit 6 of the watchdog timer control register is "0", the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note.) . When executing the WIT instruction, the watchdog timer does not stop. * When bit 6 is "1", execution of STP instruction causes an internal reset. When this bit is set to "1" once, it cannot be rewritten to "0" by program. Bit 6 is "0" at reset. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is "0": when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is "1": when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 s Note. The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. XCIN "10" Main clock division ratio selection bits (Note) "FF16" is set when watchdog timer control register is written to. Watchdog timer L (8) "0" "1" Watchdog timer H (8) Data bus "FF16" is set when watchdog timer control register is written to. 1/16 "00" "01" XIN Watchdog timer H count source selection bit STP instruction function selection bit STP instruction Reset circuit Internal reset RESET Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig 54. Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction function selection bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig 55. Structure of Watchdog timer control register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 61 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more of XIN. Then the RESET pin is returned to an "H" level (the power source voltage should be between 1.8 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.29 V for VCC of 1.8 V. Notice: This is not a final specification. Some parametric limits are subject to change. VCC RESET VCC 0V RESET 0V 1.8 V 0.29 V or less RESET VCC Power source voltage detection circuit Example at VCC = 5 V Fig 56. Reset circuit example XIN RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN : 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN) = 8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig 57. Reset sequence Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 62 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Address (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) Timer Z (low-order) (TZL) (35) Timer Z (high-order) (TZH) (36) Timer Z mode register (TZM) (37) PWM control register (PWMCON) (38) PWM prescaler (PREPWM) (39) PWM register (PWM) (40) Baud rate generator 3 (BRG3) Address 002816 002916 002A16 002B16 Register contents FF16 FF16 0016 0016 002C16 X X X X X X X X 002D16 X X X X X X X X 002F16 X X X X X X X X (41) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (42) Serial I/O3 status register (SIO3STS) (43) Serial I/O3 control register (SIO3CON) (44) UART3 control register (UART3CON) (45) AD/DA control register (ADCON) (46) AD conversion register 1 (AD1) (47) DA1 conversion register (DA1) (48) DA2 conversion register (DA2) (49) AD conversion register 2 (AD2) (50) Interrupt source selection register (INTSEL) (51) Interrupt edge selection register (INTEDGE) (52) CPU mode register (CPUM) (53) Interrupt request register 1 (IREQ1) (54) Interrupt request register 2 (IREQ2) (55) Interrupt control register 1 (ICON1) (56) Interrupt control register 2 (ICON2) (57) Port P0 pull-up control register (PULL0) (58) Port P1 pull-up control register (PULL1) (59) Port P2 pull-up control register (PULL2) (60) Port P3 pull-up control register (PULL3) (61) Port P4 pull-up control register (PULL4) (62) Port P5 pull-up control register (PULL5) (63) Port P6 pull-up control register (PULL6) (64) Processor status register (65) Program counter 003116 1 0 0 0 0 0 0 0 003216 0016 (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) 003316 1 1 1 0 0 0 0 0 003416 0 0 0 0 1 0 0 0 003516 X X X X X X X X 003616 003716 0016 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (16) Timer Y, Z count source selection register (TYZCSS) (17) MISRG 000F16 0 0 1 1 0 0 1 1 001016 0016 003816 0 0 0 0 0 0 X X 003916 003A16 0016 0016 (18) Transmit/Receive buffer register 1 (TB1/RB1) 001816 X X X X X X X X (19) Serial I/O1 status register (SIO1STS) (20) Serial I/O1 control register (SIO1CON) (21) UART1 control register (UART1CON) (22) Baud rate generator 1 (BRG1) (23) Serial I/O2 control register (SIO2CON) (24) Watchdog timer control register (WDTCON) (25) Serial I/O2 register (SIO2) (26) Prescaler 12 (PRE12) (27) Timer 1 (T1) (28) Timer 2 (T2) (29) Timer XY mode register (TM) (30) Prescaler X (PREX) (31) Timer X (TX) (32) Prescaler Y (PREY) (33) Timer Y (TY) 001916 1 0 0 0 0 0 0 0 001A16 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 (PS) (PCH) (PCL) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 XXXXX1XX FFFD16 contents FFFC16 contents 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 Note : X: Not fixed. Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig 58. Internal status at reset Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 63 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) CLOCK GENERATING CIRCUIT The 3803 group (Spec.H QzROM version) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. * Frequency Control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode The internal clock is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control Notice: This is not a final specification. Some parametric limits are subject to change. (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit (bit 0 of address 001016) is "0", the prescaler 12 is set to "FF16" and timer 1 is set to "0116". When the oscillation stabilizing time set after STP instruction released bit is "1", set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 64 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. XCIN XCOUT Rf CCIN XIN XOUT Rd (Note) Rd CCOUT CIN COUT Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies to add a feedback resistor externally to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig 59. Ceramic resonator circuit XCIN XCOUT Open XIN XOUT Open External oscillation circuit VCC VSS External oscillation circuit VCC VSS Fig 60. External clock input circuit Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 65 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. XCIN XCOUT "0" "1" Port XC switch bit XIN (Note 4) XOUT Main clock division ratio selection bits (Note 1) Low-speed mode 1/2 1/4 Divider Prescaler 12 Timer 1 High-speed or middle-speed mode (Note 3) Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode High-speed or low-speed mode Main clock stop bit Timing (internal clock) Q S R STP instruction WIT instruction S R Q QS R STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port XC switch bit (b4) to "1". 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is "0", timer 1 is set "0116" and prescaler 12 is set "FF16" automatically. When bit 0 of MISRG is "1" , set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig 61. System clock generating circuit block diagram (Single-chip mode) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 66 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Reset Middle-speed mode (f() = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM6 "1""0" High-speed mode (f() = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM4 "1""0" 4 C M " 0" "1 M 6 " C " "1 "0 " C "0 M 4 " C "1 M 6 " 1" " "0 " Middle-speed mode (f() = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM6 "1""0" "1 " 6 "1 " "0 " Low-speed mode (f() = 16 kHz) CM7=1 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM7 "1""0" C "0 M 7 C M " High-speed mode (f() = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM4 "1""0" b7 b4 CPU mode register (CPUM : address 003B16) CM5 "1""0" Low-speed mode (f() = 16 kHz) CM7=1 CM6=0 CM5=1 (8 MHz stopped) CM4=1 (32 kHz oscillating) CM4 : Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 (High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/highspeed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/ high-speed mode. 7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock. Fig 62. State transitions of system clock Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 67 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The instruction with the addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial Interface In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial I/O2 register, during transfer clock is "H". Notice: This is not a final specification. Some parametric limits are subject to change. A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A/D conversion. Do not execute the STP instruction during an A/D conversion. D/A Converter The accuracy of the D/A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC 4.0 V is recommended. When a D/A converter is not used, set all values of DAi conversion registers (i=1, 2) to "0016". Instruction Execution Time The instruction execution time is obtained by multiplying the period of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock is double of the XIN period in high-speed mode. Reserved Area, Reserved Bit Do not write any data to the reserved area in the SFR area and the special page. (Do not change the contents after reset.) CPU Mode Register Be sure to fix bit 3 of the CPU mode register (address 003B16) to "1". Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 68 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) NOTES ON USAGE Termination of Unused Pins. Be sure to perform the termination of unused pins. Notice: This is not a final specification. Some parametric limits are subject to change. (Note) The shortest Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Electric Characteristic Differences Between Flash Memory, Mask ROM and QzROM Version MCUs There are differences in the manufacturing processes and the mask pattern among flash memory, mask ROM, and QzROM version MCUs due to the differences of the ROM type. Even when the ROM type is the same, when the memory size is different, the manufacturing processes and the mask pattern differ. For these reasons, the oscillation circuit constants and the characteristics such as a characteristic value, operation margin, noise immunity, and noise radiation within the limits of electrical characteristics may differ. When manufacturing an application system, please perform sufficient evaluations in each product. Especially, when switching a product (example: change from the mask ROM version to QzROM version), please perform sufficient evaluations by the switching product in the stage before massproducing an application system. Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. QzROM Version Connect the CNVSS/VPP pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the VS S pin of the microcomputer. * Reason The CNVSS/VPP pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. CNVSS/VPP Approx. 5k VSS (Note) The shortest Note. Shows the microcomputer's pin. Fig 63. Wiring for the CNVSS/VPP Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. uses the ROM option setup data at the ROM code protect address (address FFDB16) when writing to the QzROM. Consequently, the actual written value might differ from the ordered value as the contents of the ROM code protect address. The ROM option setup data in the mask file is "0016" for protect enabled, "FE16" (protect enabled to the protect area 1 only) or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address of the QzROM product shipped after writing are "0016", "FE16" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016", "FE16" and "FF16" can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 69 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Notice: This is not a final specification. Some parametric limits are subject to change. Table 10 Absolute maximum ratings Symbol VCC VI Parameter Power source voltages Input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, VREF Input voltage P32, P33 Input voltage RESET, XIN Input voltage Output voltage CNVSS P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, XOUT P32, P33 Ta=25 C Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. Ratings -0.3 to 6.5 -0.3 to VCC + 0.3 Unit V V VI VI VI VO -0.3 to 5.8 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 V V V V VO Pd Topr Tstg Output voltage Power dissipation -0.3 to 5.8 Operating temperature Storage temperature 1000(1) -20 to 85 -65 to 125 V mW C C NOTES: 1. This value is 300 mW except SP package. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 70 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Recommended operating conditions Table 11 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Power source voltage(1) Conditions When start oscillating(2) f(XIN) 2.1 MHz High-speed mode f() = f(XIN)/2 f(XIN) 4.2 MHz f(XIN) 8.4 MHz f(XIN) 12.5 MHz f(XIN) 16.8 MHz f(XIN) 6.3 MHz f(XIN) 8.4 MHz f(XIN) 12.5 MHz f(XIN) 16.8 MHz Notice: This is not a final specification. Some parametric limits are subject to change. Symbol VCC Limits Min. 2.2 2.0 2.2 2.7 4.0 4.5 1.8 2.2 2.7 4.5 0.85 VCC 0.8 VCC Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC Unit V V Middle-speed mode f() = f(XIN)/8 V VSS VIH VIH VIH Power source voltage "H" input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 "H" input voltage P32, P33 "H" input voltage RESET, XIN, XCIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" input voltage RESET, CNVSS "L" input voltage XIN, XCIN Main clock input oscillation frequency(3) 1.8 VCC < 2.7 V 2.7 VCC 5.5 V V V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 0.85 VCC 0.8 VCC 0.85 VCC 0.8 VCC 0 0 5.5 5.5 VCC VCC 0.16 VCC 0.2 VCC V V VIL V VIL VIL f(XIN) 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC 5.5 V High-speed mode f() = f(XIN)/2 2.0 VCC < 2.2 V 2.2 VCC < 2.7 V 2.7 VCC < 4.0 V 4.0 VCC < 4.5 V 4.5 VCC 5.5 V 1.8 VCC < 2.2 V 2.2 VCC < 2.7 V 2.7 VCC < 4.5 V 4.5 VCC 5.5 V 0 0 0 0.16 VCC 0.2 VCC 0.16 VCC ( 20 x VCC - 36 ) x 1.05 ----------------------------------------------------------2 ( 24 x VCC - 40.8 ) x 1.05 ---------------------------------------------------------------3 ( 9 x VCC - 0.3 ) x 1.05 --------------------------------------------------------3 ( 24 x VCC - 60 ) x 1.05 ----------------------------------------------------------3 V V MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz 16.8 ( 15 x VCC - 9 ) x 1.05 ------------------------------------------------------3 ( 24 x VCC - 28.8 ) x 1.05 ---------------------------------------------------------------3 ( 15 x VCC + 39 ) x 1.1 -------------------------------------------------------7 16.8 Middle-speed mode f() = f(XIN)/8 f(XCIN) Sub-clock input oscillation frequency(3, 4) 32.768 50 NOTES: 1. When using A/D converter, see A/D converter recommended operating conditions. 2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. 3. When the oscillation frequency has a duty cycle of 50%. 4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 71 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 12 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Parameter "H" total peak output current(1) "H" total peak output current(1) "L" total peak output "L" total peak output current(1) current(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37 P20-P27 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37 P20-P27 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 Min. Limits Typ. Max. -80 -80 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 80 80 80 -40 -40 "L" total peak output current(1) "H" total average output current(1) "H" total average output current(1) "L" total average output "L" total average output current(1) current(1) 40 40 40 -10 "L" total average output current(1) "H" peak output current(2) "L" peak output current(2) "L" peak output current(2) "H" average output current(3) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) 10 20 -5 "L" average output current(3) "L" average output current(3) 5 10 NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 72 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Electrical characteristics Notice: This is not a final specification. Some parametric limits are subject to change. Table 13 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" output voltage P20-P27 Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 1.8 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V IOL = 20 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V Min. VCC - 2.0 VCC - 1.0 2.0 1.0 2.0 0.4 0.4 0.5 0.5 VI = VCC (Pin floating, Pull-up transistor "off") VI = VCC VI = VCC VI = VCC (Pin floating, Pull-up transistor "off") VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped -80 -30 -4.0 -210 -70 -420 -140 Limits Typ. Max. Unit V VOL V VOL V VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL IIL IIL Hysteresis CNTR0, CNTR1, CNTR2, INT0-INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" input current RESET, CNVSS "L" input current XIN "L" input current (at Pull-up) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 RAM hold voltage V V V 5.0 A 5.0 4.0 -5.0 A A A -5.0 A A A VRAM 1.8 VCC V NOTES: 1. P35 is measured when the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". P45 is measured when the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 73 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 14 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = -20 to 85 C, f(XCIN)=32.768kHz (Stopped in middle-speed mode), Output transistors "off", AD converter not operated) Symbol ICC Parameter Power source High-speed current mode Test conditions VCC = 5.0 V f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 C Ta = 85 C f(XIN) = 16.8 MHz, VCC = 5.0 V In Middle-, high-speed mode Min. Limits Typ. 8.0 6.5 5.0 2.5 2.0 1.9 1.0 0.6 4.0 3.0 2.5 1.8 1.5 1.2 1.0 55 40 15 8 6 3 0.1 500 Max. 15.0 12.0 9.0 5.0 3.6 3.8 2.0 1.2 7.0 6.0 5.0 3.3 3.0 2.4 2.0 200 70 40 15 15 6 1.0 10 Unit mA VCC = 3.0 V mA Middle-speed mode VCC = 5.0 V mA VCC = 3.0 V mA Low-speed mode VCC = 5.0 V VCC = 3.0 V VCC = 2.0 V A A A A A In STP state (All oscillation stopped) Increment when A/D conversion is executed Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 74 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) A/D converter characteristics Notice: This is not a final specification. Some parametric limits are subject to change. Table 15 A/D converter recommended operating conditions (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VREF AVSS VIA f(XIN) Parameter Power source voltage (When A/D converter is used) Analog convert reference voltage Analog power source voltage Analog input voltage AN0-AN15 Main clock input oscillation frequency (When A/D converter is used) Conditions 8-bit A/D mode(1) 10-bit A/D mode(2) Limits Min. 2.0 2.2 2.0 0 2.0 VCC < 2.2 V 2.2 VCC < 2.7 V 2.7 VCC < 4.0 V 4.0 VCC < 4.5 V 4.5 VCC 5.5 V 0 0.5 0.5 0.5 0.5 0.5 VCC ( 20 x VCC - 36 ) x 1.05 ----------------------------------------------------------2 ( 24 x VCC - 40.8 ) x 1.05 ---------------------------------------------------------------3 ( 9 x VCC - 0.3 ) x 1.05 --------------------------------------------------------3 ( 24.6 x VCC - 62.7 ) x 1.05 --------------------------------------------------------------------3 Typ. 5.0 5.0 Max. 5.5 5.5 VCC Unit V V V V MHz 16.8 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is "1". 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is "0". Table 16 A/D converter characteristics (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol - - Parameter Resolution Absolute accuracy (excluding quantization error) Test conditions 8-bit A/D mode(1) 10-bit A/D mode(2) 8-bit A/D mode(1) 10-bit A/D mode(2) 2.0 VREF < 2.2 V 2.2 VREF 5.5 V 2.2 VREF < 2.7 V 2.7 VREF 5.5 V Min. Limits Typ. Max. 8 10 3 2 5 4 50 61 Unit bit LSB LSB 2tc(XIN) k A A A tCONV RLADDER IVREF II(AD) Conversion time 8-bit A/D mode(1) mode(2) 12 50 35 150 10-bit A/D Ladder resistor Reference power at A/D converter operated VREF = 5.0 V source input current at A/D converter stopped VREF = 5.0 V A/D port input current 100 200 5.0 5.0 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is "1". 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is "0". D/A converter characteristics Table 17 D/A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol - - Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current(1) Min. Limits Typ. 4.0 VREF 5.5 V 2.7 VREF < 4.0 V 2 3.5 tsu RO IVREF Max. 8 1.0 2.5 3 5 3.2 Unit bit % s k mA NOTES: 1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being "0016". Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 75 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Timing requirements and switching characteristics Notice: This is not a final specification. Some parametric limits are subject to change. Table 18 Timing requirements (1) (VCC = 2.0 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Parameter Reset input "L" pulse width Main clock XIN input cycle time Limits Min. 16 59.5 10000/(86 VCC - 219) 26 x 103/(82 VCC - 3) 10000/(84 VCC - 143) 10000/(105 VCC - 189) 25 4000/(86 VCC - 219) 10000/(82 VCC - 3) 4000/(84 VCC - 143) 4000/(105 VCC - 189) 25 4000/(86 VCC - 219) 10000/(82 VCC - 3) 4000/(84 VCC - 143) 4000/(105 VCC - 189) 20 5 5 120 160 250 500 1000 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 Typ. Max. Unit XIN cycle ns 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V tWH(XIN) Main clock XIN input "H" pulse width ns tWL(XIN) Main clock XIN input "L" pulse width ns tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) Sub-clock XCIN input cycle time Sub-clock XCIN input "H" pulse width Sub-clock XCIN input "L" pulse width CNTR0-CNTR2 input cycle time s s s tWH(CNTR) CNTR0-CNTR2 input "H" pulse width tWL(CNTR) CNTR0-CNTR2 input "L" pulse width tWH(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "H" pulse width tWL(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "L" pulse width 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V ns ns ns ns ns Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 76 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 19 Timing requirements (2) (VCC = 2.0 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol tC(SCLK1) tC(SCLK3) Serial I/O1, serial I/O3 clock input cycle time(1) Parameter 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V Min. 250 320 500 1000 2000 120 150 240 480 950 120 150 240 480 950 70 90 100 200 400 32 40 50 100 200 500 650 1000 2000 4000 200 260 400 950 2000 200 260 400 950 2000 100 130 200 400 800 100 130 150 300 600 Limits Typ. Max. Unit ns tWH(SCLK1) tWH(SCLK3) Serial I/O1, serial I/O3 clock input "H" pulse width(1) ns tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock input "L" pulse width(1) ns tsu(RxD1-SCLK1) tsu(RxD3-SCLK3) Serial I/O1, serial I/O3 clock input setup time ns th(SCLK1-RxD1) th(SCLK3-RxD3) Serial I/O1, serial I/O3 clock input hold time ns tC(SCLK2) Serial I/O2 clock input cycle time ns tWH(SCLK2) Serial I/O2 clock input "H" pulse width ns tWL(SCLK2) Serial I/O2 clock input "L" pulse width ns tsu(SIN2-SCLK2) Serial I/O2 clock input setup time ns th(SCLK2-SIN2) Serial I/O2 clock input hold time ns NOTES: 1. When bit 6 of address 001A16 and bit 6 of address 003216 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are "0" (UART). Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 77 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 20 Switching characteristics (1) (VCC = 2.0 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWH(SCLK3) Parameter Serial I/O1, serial I/O3 clock output "H" pulse width 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V Test conditions Limits Min. tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 tC(SCLK1)/2-45, tC(SCLK3)/2-45 tC(SCLK1)/2-50, tC(SCLK3)/2-50 tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 tC(SCLK1)/2-45, tC(SCLK3)/2-45 tC(SCLK1)/2-50, tC(SCLK3)/2-50 Typ. Max. Unit ns tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock output "L" pulse width ns td(SCLK1-TxD1) td(SCLK3-TxD3) Serial I/O1, serial I/O3 output delay time(1) 140 200 350 400 420 -30 -30 -30 -30 -30 ns tV(SCLK1-TxD1) tV(SCLK3-TxD3) Serial I/O1, serial I/O3 output valid time(1) ns tr(SCLK1) tr(SCLK3) Serial I/O1, serial I/O3 rise time of clock output tf(SCLK1) tf(SCLK3) Serial I/O1, serial I/O3 fall time of clock output Fig.64 30 35 40 45 50 30 35 40 45 50 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 tC(SCLK2)/2-260 tC(SCLK2)/2-280 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 tC(SCLK2)/2-260 tC(SCLK2)/2-280 200 250 300 350 400 0 0 0 0 0 ns ns tWH(SCLK2) Serial I/O2 clock output "H" pulse width ns tWL(SCLK2) Serial I/O2 clock output "L" pulse width ns td(SCLK2-SOUT2) Serial I/O2 output delay time ns tV(SCLK2-SOUT2) Serial I/O2 output valid time ns NOTES: 1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 78 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Table 21 Switching characteristics (2) (VCC = 2.0 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol tf(SCLK2) Parameter Serial I/O2 fall time of clock output 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V 4.5 VCC 5.5 V 4.0 VCC < 4.5 V 2.7 VCC < 4.0 V 2.2 VCC < 2.7 V 2.0 VCC < 2.2 V Test conditions Limits Min. Typ. Max. 30 35 40 45 50 30 35 40 45 50 30 35 40 45 50 Unit ns tr(CMOS) CMOS rise time of output(1) Fig.64 tf(CMOS) CMOS fall time of output(1) 10 12 15 17 20 10 12 15 17 20 ns ns NOTES: 1. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 79 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Measurement output pin 100pF Measurement output pin 1k 100pF CMOS output N-channel open-drain output Fig 64. Circuit for measuring output switching characteristics (1) Fig 65. Circuit for measuring output switching characteristics (2) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 80 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. Single-chip mode timing diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 CNTR2 0.8VCC INT1, INT2, INT3 INT00, INT40 INT01, INT41 tWH(INT) 0.8VCC 0.2VCC tWL(INT) tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(XCIN) tWH(XCIN) tWL(XCIN) 0.2VCC XCIN 0.8VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) SCLK1 SCLK2 SCLK3 RXD1 RXD3 SIN2 tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) 0.2VCC tsu(RXD1-SCLK1), tsu(SIN2-SCLK2), tsu(RXD3-SCLK3) 0.8VCC 0.2VCC tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) 0.8VCC th(SCLK1-RXD1), th(SCLK2-SIN2), th(SCLK3-RXD3) td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3) TXD1 TXD3 SOUT2 Fig 66. Timing diagram (in single-chip mode) Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 81 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) PACKAGE OUTLINE JEITA Package Code P-SDIP64-17x56.4-1.78 RENESAS Code PRDP0064BA-A Previous Code 64P4B MASS[Typ.] 7.9g Notice: This is not a final specification. Some parametric limits are subject to change. 64 33 *1 e1 E *2 D A A2 c 1 32 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Symbol Dimension in Millimeters L SEATING PLANE e *3 b3 bp *3 b2 e1 D E A A1 A2 bp b2 b3 c e L Min 18.75 56.2 16.85 0.38 0.4 0.65 0.9 0.2 0 1.528 2.8 Nom 19.05 56.4 17.0 Max 19.35 56.6 17.15 5.08 A1 3.8 0.5 0.6 0.75 1.05 1.0 1.3 0.25 0.32 15 1.778 2.028 JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 49 32 HE E Reference Symbol *2 c1 Dimension in Millimeters c 64 ZE 17 Terminal cross section 1 Index mark ZD 16 F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom 10.0 10.0 1.4 11.8 12.0 11.8 12.0 0.05 0.15 0.09 0 Min 9.9 9.9 Max 10.1 10.1 e *3 A1 y bp L L1 Detail F x 0.35 12.2 12.2 1.7 0.1 0.15 0.20 0.25 0.18 0.145 0.20 0.125 8 0.5 0.08 0.08 1.25 1.25 0.5 0.65 1.0 A2 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 82 of 91 A c PRELIMINARY 3803 Group (Spec.H QzROM version) Notice: This is not a final specification. Some parametric limits are subject to change. JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 48 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 49 32 bp b1 c1 HE E c Reference Symbol *2 Dimension in Millimeters Terminal cross section 64 17 1 ZD Index mark 16 F L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 bp x Detail F Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 ZE A A2 Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 83 of 91 A1 c PRELIMINARY 3803 Group (Spec.H QzROM version) APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. Notice: This is not a final specification. Some parametric limits are subject to change. Set D flag to "1" ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Reset Fig 3. Initializing of flags Execution of decimal calculations Main program 4. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 5. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. 6. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The instruction with the addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. 7. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the 740 Family Software Manual. The frequency of the internal clock is the twice the XIN cycle in high-speed mode, 8 times the XIN cycle in middle-speed mode, and the twice the XCIN in low-speed mode. 8. Reserved Area, Reserved Bit Do not write any data to the reserved area in the SFR area and the special page. (Do not change the contents after reset.) 9. CPU Mode Register Be sure to fix bit 3 of the CPU mode register (address 003B16) to "1". Fig 1. Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. (S) (S) + 1 Stored PS Fig 2. Stack memory contents after PHP instruction execution 2. BRK instruction (1) Interrupt priority level When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. * Interrupt request bit and interrupt enable bit are set to "1". * Interrupt disable flag (I) is set to "1" to disable interrupt. 3. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to "1" before each calculation. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 84 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state In standby state*1 for low-power dissipation, do not make input levels of an I/O port "undefined". Even when an I/O port of Nchannel open-drain is set as output mode, if output data is "1", the aforementioned notes are necessary. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external Notice: This is not a final specification. Some parametric limits are subject to change. Termination of Unused Pins 1. Terminate unused pins (1) Output ports : Open (2) I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (3) The AVSS pin when not using the A/D converter : * When not using the A/D converter, handle a power source pin for the A/D converter, AVSS pin as follows: AVSS: Connect to the VSS pin. 2. Termination remarks (1) I/O ports : Do not open in the input mode. NOTES: 1. Standby state : stop mode by executing STP instruction wait mode by executing WIT instruction 2. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. NOTES: 2. Bit managing instructions : SEB, and CLB instructions Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 85 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. * Interrupt edge selection register (address 003A16) * Timer XY mode register (address 002316) * Timer Z mode register (address 002A16) Set the above listed registers or bits as the following sequence. Notice: This is not a final specification. Some parametric limits are subject to change. 2. Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to "0", execute one or more instructions before executing the BBC or BBS instruction. Clear the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Set the corresponding interrupt enable bit to "0" (disabled). Execute the BBC or BBS instruction Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to "1". Fig 5. Sequence of check of interrupt request bit NOP (one or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig 4. Sequence of changing relevant register Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 86 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notes on 8-bit Timer (timer 1, 2, X, Y) * If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. * Set the double-function port of the CNTR0/CNTR1 pin and port P54/P55 to output in the pulse output mode. * Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to input in the event counter mode and the pulse width measurement mode. Notice: This is not a final specification. Some parametric limits are subject to change. 5. Programmable one-shot generating mode * Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. * This mode cannot be used in low-speed mode. * If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. 6. All modes * Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation "writing data only to the latch" is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation "writing data to both the latch and the timer at the same time" is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. * Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. * Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. * Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Notes on 16-bit Timer (timer Z) 1. Pulse output mode * Set the double-function port of the CNTR2 pin and port P47 to output. 2. Pulse period measurement mode * Set the double-function port of the CNTR2 pin and port P47 to input. * A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). * Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. * "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. 3. Pulse width measurement mode * Set the double-function port of the CNTR2 pin and port P47 to input. * A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). * Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. * "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. 4. Programmable waveform generating mode * Set the double-function port of the CNTR2 pin and port P47 to output. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 87 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notes on Serial Interface 1. Notes when selecting clock synchronous serial I/O (1) Stop of transmission operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to "0" (serial I/Oi and transmit disabled). Notice: This is not a final specification. Some parametric limits are subject to change. 3. SRDYi (i = 1, 3) output of reception side When signals are output from the SRDYi pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/Oi (i = 1, 3) control register again Set the serial I/Oi control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Fig 6. Sequence of setting serial I/Oi (i = 1, 3) control register again 5. Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit buffer register at "H" of the SCLKi input level. 7. Transmit interrupt request when transmit enable bit is set When using the transmit interrupt, take the following sequence. (1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to "0" (disabled). (2) Set the tranasmit enable bit to "1". (3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to "0" after 1 or more instruction has executed. (4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to "1" (enabled). Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 88 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notes on PWM The PWM starts from "H" level after the PWM enable bit is set to enable and "L" level is temporarily output from the PWM pin. The length of this "L" level output is as follows: n+1 2 * f(XIN) n+1 f(XIN) (s) (s) (Count source selection bit = "0", where n is the value set in the prescaler) (Count source selection bit = "1", where n is the value set in the prescaler) Notice: This is not a final specification. Some parametric limits are subject to change. Notes on Watchdog Timer * Make sure that the watchdog timer H does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. * When the STP instruction disable bit has been set to "1", it is impossible to switch it to "0" by a program. Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, be sure to verify the operation of application products on the user side. Notes on RESET Pin Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : * Make the length of the wiring which is connected to a capacitor as short as possible. * Be sure to verify the operation of application products on the user side. XCIN Rf XCOUT Rd CCIN CCOUT Fig 7. Ceramic resonator circuit Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 89 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) Notes on Restarting Oscillation * Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = "0116", Prescaler 12 = "FF16") are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by writing "1" to bit 0 of MISRG (address 001016). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Notice: This is not a final specification. Some parametric limits are subject to change. Notes on Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Electric Characteristic Differences Between Flash Memory, Mask ROM and QzROM Version MCUs There are differences in the manufacturing processes and the mask pattern among flash memory, mask ROM, and QzROM version MCUs due to the differences of the ROM type. Even when the ROM type is the same, when the memory size is different, the manufacturing processes and the mask pattern differ. For these reasons, the oscillation circuit constants and the characteristics such as a characteristic value, operation margin, noise immunity, and noise radiation within the limits of electrical characteristics may differ. When manufacturing an application system, please perform sufficient evaluations in each product. Especially, when switching a product (example: change from the mask ROM version to QzROM version), please perform sufficient evaluations by the switching product in the stage before massproducing an application system. Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 90 of 91 PRELIMINARY 3803 Group (Spec.H QzROM version) QzROM Version Connect the CNVSS/VPP pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the VS S pin of the microcomputer. * Reason The CNVSS/VPP pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. Notice: This is not a final specification. Some parametric limits are subject to change. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the mask option setup data in the mask file which is submitted at ordering. Renesas Technology corp. uses the mask option setup data at the ROM code protect address (address FFDB16) when writing to the QzROM. Consequently, the actual written value might differ from the ordered value as the contents of the ROM code protect address. The ROM option setup data in the mask file is "0016" for protect enabled, "FE16" (protect enabled to the protect area 1 only) or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address of the QzROM product shipped after writing are "0016", "FE16" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016", "FE16" and "FF16" can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. (Note) The shortest CNVSS/VPP Approx. 5k VSS (Note) The shortest Note. Shows the microcomputer's pin. Fig 8. Wiring for the CNVSS/VPP Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Rev.1.10 Nov 14, 2005 REJ03B0166-0110 Page 91 of 91 REVISION HISTORY Rev. 1.00 1.10 Date Page Sep. 30, 2005 Nov. 14, 2005 - 3803 Group (Spec.H QzROM version) Data Sheet Description Summary First edition issued Fig 14. Port block diagram (3) (18) Port P56 revised Fig 54. Block diagram of Watchdog timer; STP instruction disable bit STP instruction function selection bit revised QzROM version; approximately 1 k to 5 k resistor approximately 5 k resistor Fig 47. Wiring for the CNVSS/VPP added Notes On QzROM Writing Orders; (extension: .mask) (extension: .msk) revised 20 61 69 82-83 84-91 Package Outline revised Appendix added (1/1) |
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